Integrated circuits ("ICs") fabricated with CMOS transistors advantageously consume little DC current and are readily produced. Unfortunately, however, CMOS transistors are susceptible to a phenomenon known as "latch-up".
By way of example, FIG. 1A depicts a generic CMOS inverter 10 coupled between the upper and lower power supplies, VDD and VSS. The inverter includes a P-type or PMOS transistor M1 and an N-type or NMOS transistor M2. The gates of M1 and M2 are coupled together to an input port that receives a V.sub.IN signal, and the source of M1 and the drain of M2 are coupled together to an output port that provides a V.sub.OUT signal that is an inversion of VIN. The drain of M1 is coupled to VDD and the source of M2 is coupled to VSS, which is commonly ground.
Under normal operation, V.sub.OUT is an inverted version of VIN, and under DC or static conditions, essentially no dissipation within the transistors occurs since when M1 is turned on, M2 is turned off, and vice versa. Under static load conditions, the current i.sub.o provided by the upper power supply V.sub.DD typically is limited to approximately V.sub.DD /R.sub.L, where R.sub.L is the resistive component of the load being driven by inverter 10.
FIG. 1B is a simplified cross-section of a P-type substrate upon which inverter 10 has been fabricated. PMOS transistor M1 is fabricated with an N well and includes two spaced-apart P+ regions that define M1's source and drain, and a gate that overlies and is separated from the spaced-apart region by a thin oxide layer. NMOS transistor M2 includes two spaced-apart N+ regions that define M2's source and drain, and a gate that overlies and is separated from the spaced-apart region by a thin oxide layer.
As shown in FIG. 1B, M1's P+ drain region is coupled to VDD, M1's P+ source region is coupled to VOUT and to M2's N+ drain region, and the gates of M1 and M2 are coupled together to receive a VIN signal. M2's N+ source region is coupled to the lower power supply VSS. While the above-described configuration defines a series-coupled PMOS and NMOS transistor pair, the various doped regions also define parasitic bipolar transistors Q1 and Q2, drawn in phantom. It is the inherent presence of Q1 and Q2 that give rise to latch-up failure in CMOS circuits such as inverter 10.
PNP bipolar transistor Q1 is defined by a P+ doped emitter region (e.g., the P+ drain of M1), an N doped base region (e.g., the N well containing PMOS transistor M1), and a P doped collector region (e.g., the P substrate). NPN bipolar transistor Q2 is defined by an N doped collector region (e.g., the N well containing PMOS transistor M1), and P doped base region (e.g., the P substrate), and an N doped emitter region (e.g., the N+ source of NMOS transistor M2). Similarly, conductive paths may exist defining resistors R1 and R2, respectively coupled across Q1's emitter-base junction, and across Q2's emitter base junction.
Latch-up can occur during operation of inverter 10 when parasitic bipolar transistors Q1 and Q2 are both forward biased, and thus turned-on. The resultant NPN-PNP configuration will be recognized as being equivalent to a silicon-controlled rectifier ("SCR"). Like a true SCR, once the parasitic bipolar transistors Q1-Q2 turn-on, they can only be turned-off by removing all operating power from inverter 10.
Latch-up current from VDD through Q1, Q2 to VSS can readily reach an ampere or so, within a few hundred nanoseconds or less. As such, latch-up current is far in excess of the nominal load current i.sub.o associated with inverter 10. The resultant high latch-up current flow and attendant heat can damage or destroy inverter 10 (or other CMOS circuit) before it is even known to interrupt the power supply. Of course, in actual applications, interrupting operating power to inverter 10 will also interrupt operating power to many other ICs as well, further hampering performance of the system containing the ICs.
In designing inverter CMOS circuits such as inverter 10, it is known to reduce latch-up by keeping the current gain .beta. for bipolar transistors Q1 and Q2 low, and by keeping the bulk resistance of the substrate high. However in designing new CMOS ICs to avoid latch-up, the rapidity with which latch-up destruction can occur hampers the analysis procedure. It is to be understood that the inverter of FIG. 1A is but one example of a CMOS-implemented circuit that is susceptible to latch-up. However, non-inverter CMOS circuits can also be susceptible to such damage.
It will be appreciated from FIG. 1B that latch-up is characterized by forward biased emitter-base junctions for the parasitic bipolar transistors Q1 and Q2. Under high current latch-up conditions, these emitter-bias junctions emit photons. These photo emissions can be examined using an emission microscope, in an attempt to analyze the latch-up problem with a view to modifying the IC layout or design to avoid future latch-up.
Understandably, it is difficult to intentionally cause latch-up in a predictable fashion for purposes of observing and analyzing the phenomenon. For example, in testing signal pins of a CMOS device for latch-up, it is necessary to provide a test generator that outputs a first pulse train that is coupled to the power pin of the device under test, and a second pulse train that is coupled to a signal pin on the device under test. During a time when the first pulse train is "high", a pulse from the second pulse train can trigger latch-up.
In power pin testing, a single composite pulse train is coupled to the power pin of the CMOS device under test. When it is not "low", the composite pulse train has a first voltage level approximating a level of the first pulse train. Superimposed on a portion of the first voltage level is a trigger pulse having a higher voltage level approximating the trigger pulse level of the second pulse train.
One partial solution to latch-up testing was put forth by the Japanese Hamamatsu company. Hamamatsu provided a system that included a dedicated digital delay and pulse generator (their model DG535), a latch-up pulse generator, and a gate controlled camera. This system output first and second pulse trains for signal pin latch-up testing, but did not provide a composite pulse for power pin testing. The second pulse train (the trigger pulse train) was apparently output by charging and discharging one or more capacitors. This use of capacitors had the unfortunate result that the pulse width of the trigger pulse could not readily be user controlled. The system did, however, allow variation in the delay between the trigger pulse and the first pulse train, and in the amplitude of the pulse trains.
This system was designed for use with a Hamamatsu emission microscope whose images of a CMOS device in latch-up would be photographed in synchronism with operation of the gate controlled camera. The DG535 controllably output synchronization trigger pulses to the latch-up generator and to the camera control gate. Apparently under certain conditions, signal-pin latch-up in the device under test could be induced, whereupon the gate controlled camera could record emission microscope images for later analysis of any latch-up.
In short, the Hamamatsu system was essentially dedicated for use with the gate controlled camera, and associated emission microscope. The system did not meet Joint Electronic Device Engineering Committee ("JEDEC") standards, in that there was no provision for power pin latch-up testing. Although signal pin testing was possible, essentially no user control over the width of the second pulse train (trigger pulse) was provided. Finally, the cost of the Hamamatsu apparatus was relatively high, as much as $5,000 for the SG535 digital delay generator alone.
Thus, there is a need for a latch-up pulse generator system that outputs pulses for power pin testing as well as signal pin testing of a CMOS device, according to present JEDEC standards. Such generator should permit user control over width, delay, and amplitude of the trigger pulse to promote latch-up sensitivity evaluation.
The system should be self-contained and permit latch-up analysis with essentially any type of emission microscope. Finally, such system should cost substantially less than several thousand dollars to implement.
The present invention discloses such a system.